Georgios Keramidas
Dr. Georgios Keramidas received his PhD degree in Electrical and
Computer Engineering from the University of Patras, Greece. He is currently an Assistant
Professor at the School of Informatics at the Aristotle University of Thessaloniki. Dr
Keramidas’ main research interests are in the areas of low-power processor/memory design,
multicore systems, VLIW/multi-threaded architectures, network and graphic processors,
reconfigurable systems, power modelling methodologies, FPGA prototyping, and compiler
optimizations techniques. He has published more than 85 papers, two books, three book
chapters and he also holds 16 US and Chinese patents (4 more patents are under
evaluation). His work received more than 1280 citations (h-index: 17, i10-index: 27) and a
best-paper award. During the last years, Dr Keramidas has participated in more than 10
collaborative research projects funded by European Commission and in five national projects
either as project coordinator, technical coordinator, work packager leader, or as senior
researcher. Before joining the Aristotle University, Dr. Keramidas spent almost 11 years in
industry in the position of Chief Scientific Officer of Think Silicon S.A. working in embedded,
ultra-low power multithreaded Graphics Processing Units (GPUs). He was also responsible
for running the funded projects of the company and for expanding the patent portfolio of the
company. Dr. Keramidas continues to work in the company as technology consultant.
The Era of Domain Specific Processor Architectures
Designing domain specific architectures and accelerators for modern
applications is the only way to deal with the latency, power consumption, and reliability
requirements dictated by these applications. In this presentation, we will present the design
principles of the edge and cloud architectures and we showcase the need to execute various
modern applications at the edge. We will present the basic principles of CMOS power
consumption for cloud and edge devices and we will concentrate on the requirements for
building dedicated accelerators for graphics and TinyML applications. In both cases, a
Software (SW) – Hardware (HW) codesign approach will be followed targeting to achieve
ultra low power execution for far edge devices. Various SW/HW/compiler level low power
techniques will be presented that are employed in the Graphics and AI products of Think
Silicon, An Applied Materials Company.
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